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Buck DC to DC Converter - save and regenerate waveforms

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This design is a copy of Mike Donnelly's Buck DC to DC Converter modified to demonstrate data reduction for downloaded waveforms. For more information about the buck converter you can find Mike's design athttps://www.systemvision.com/design/buck-dc-dc-converter-switchingThis design ramps up internal voltages for a simplified model of softstart. Mike's load transient is timed to activate after steady state. The L1 current rises after an initial spike. This current charges the output cap to generate a rising output voltage. That output voltage rises past the 5V setpoint until steady state sets in around 5.5V. After that Vout settles back to its steady state level. The load transient triggers disturbances in Vout at both edges of the transient.For further analysis of steady state and line/load transients, an x-sampling voltage source is added to reduce the size of the .csv data and to skip over startup. Data reduced files are generated in an Excel post-processing session based on the x-sampling voltage peaks.The reduced data can be read back into SystemVision or other appllications to display the waveforms,compare them to waveforms from another source or use them as sources in further simulations.

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Buck DC to DC Converter - save and regenerate waveforms

ilya
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5 years 11 months

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This design is a copy of Mike Donnelly's Buck DC to DC Converter modified to demonstrate data reduction for downloaded waveforms. For more information about the buck converter you can find Mike's design athttps://www.systemvision.com/design/buck-dc-dc-converter-switchingThis design ramps up internal voltages for a simplified model of softstart. Mike's load transient is timed to activate after steady state. The L1 current rises after an initial spike. This current charges the output cap to generate a rising output voltage. That output voltage rises past the 5V setpoint until steady state sets in around 5.5V. After that Vout settles back to its steady state level. The load transient triggers disturbances in Vout at both edges of the transient.For further analysis of steady state and line/load transients, an x-sampling voltage source is added to reduce the size of the .csv data and to skip over startup. Data reduced files are generated in an Excel post-processing session based on the x-sampling voltage peaks.The reduced data can be read back into SystemVision or other appllications to display the waveforms,compare them to waveforms from another source or use them as sources in further simulations.

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Buck DC to DC Converter - save and regenerate waveforms

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Designer138341

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6 years 8 months

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This design is a copy of Mike Donnelly's Buck DC to DC Converter modified to demonstrate data reduction for downloaded waveforms. For more information about the buck converter you can find Mike's design athttps://www.systemvision.com/design/buck-dc-dc-converter-switchingThis design ramps up internal voltages for a simplified model of softstart. Mike's load transient is timed to activate after steady state. The L1 current rises after an initial spike. This current charges the output cap to generate a rising output voltage. That output voltage rises past the 5V setpoint until steady state sets in around 5.5V. After that Vout settles back to its steady state level. The load transient triggers disturbances in Vout at both edges of the transient.For further analysis of steady state and line/load transients, an x-sampling voltage source is added to reduce the size of the .csv data and to skip over startup. Data reduced files are generated in an Excel post-processing session based on the x-sampling voltage peaks.The reduced data can be read back into SystemVision or other appllications to display the waveforms,compare them to waveforms from another source or use them as sources in further simulations.

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Managing PWM Waveforms - Buck Converter

Dagi
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Dagi

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To demonstrate data reduction in a PWM design I've copied and modified Mike Donnelly's Buck DC to DC Converter at https://www.systemvision.com/design/buck-dc-dc-converter-switchingI've added a simplified softstart to simulate startup. Sofstart is implemented by ramping up internal voltages over a 5ms period after a 0.5ms delay for a total startup time of 5.5ms. Mike's load transient is timed to activate after steady state. A line transient can be simulated by adding a pulsed voltage source in series with v_line.The total time to simulate startup, steady state and the load transient is set to 10.5ms of which only the final 4ms involve the response to the transient disturbance. Downloaded .csv files of the output voltage (v_out_buck), inductor current (l1inductor/i), or any other signal cover over 84,000 time points.For a 40us switching cycle, a 1us resolution samples each switching cycle 40 times and requires only 4,000 time points to cover the steady state and load transient response. A voltage source is included in the design to mark off this sampling resolution with a sawtooth signal that starts at 6.5ms. The sawtooth appears at the net named x_smpl. Downloading x_smpl along with v_out_buck to Excel enables edits that reduce the original 84,000 time points to 4,000.To demonstrate the data reduction technique for large .csv downloads,t he design includes a dedicated table voltage source which has been preloaded with a set of 4,000 samples from an earlier simulation. The voltage signal vout_reduced displays those 4,000 samples. The table voltage source can be edited to insert to store reduced data records of any transient response generated by this buck converter.Copies of the table voltage source can be placed into this or any other design in order to display the transient response or apply it to another simulation. This mechanism can be used to test designs that are driven by the buck converter output for their ability to withstand the transient disturbance. Other simulations can be used to compare the simulated response to measured data or to analyze the simulated transient response.Watch for an accompanying blog that will explain how the table voltage source works.

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Buck Converter - sampled waveforms

Norm
Designer43361

Norm

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8 years

328

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Description

This design is a copy of Mike Donnelly's Buck DC to DC Converter modified to demonstrate data reduction for downloaded waveforms. For more information about the buck converter you can find Mike's design athttps://www.systemvision.com/design/buck-dc-dc-converter-switchingThis design ramps up internal voltages for a simplified model of softstart. Mike's load transient is timed to activate after steady state. The L1 current rises after an initial spike. This current charges the output cap to generate a rising output voltage. That output voltage rises past the 5V setpoint until steady state sets in around 5.5V. After that Vout settles back to its steady state level. The load transient triggers disturbances in Vout at both edges of the transient.For further analysis of steady state and line/load transients, an x-sampling voltage source is added to reduce the size of the .csv data and to skip over startup. Data reduced files are generated in an Excel post-processing session based on the x-sampling voltage peaks.The reduced data can be read back into SystemVision or other appllications to display the waveforms,compare them to waveforms from another source or use them as sources in further simulations.

About text formats

Managing PWM Waveforms - Buck Converter

Norm
Designer43361

Norm

Member for

8 years

328

designs

2

groups

Description

To demonstrate data reduction in a PWM design I've copied and modified Mike Donnelly's Buck DC to DC Converter at https://www.systemvision.com/design/buck-dc-dc-converter-switchingI've added a simplified softstart to simulate startup. Sofstart is implemented by ramping up internal voltages over a 5ms period after a 0.5ms delay for a total startup time of 5.5ms. Mike's load transient is timed to activate after steady state. A line transient can be simulated by adding a pulsed voltage source in series with v_line.The total time to simulate startup, steady state and the load transient is set to 10.5ms of which only the final 4ms involve the response to the transient disturbance. Downloaded .csv files of the output voltage (v_out_buck), inductor current (l1inductor/i), or any other signal cover over 84,000 time points.For a 40us switching cycle, a 1us resolution samples each switching cycle 40 times and requires only 4,000 time points to cover the steady state and load transient response. A voltage source is included in the design to mark off this sampling resolution with a sawtooth signal that starts at 6.5ms. The sawtooth appears at the net named x_smpl. Downloading x_smpl along with v_out_buck to Excel enables edits that reduce the original 84,000 time points to 4,000.To demonstrate the data reduction technique for large .csv downloads,t he design includes a dedicated table voltage source which has been preloaded with a set of 4,000 samples from an earlier simulation. The voltage signal vout_reduced displays those 4,000 samples. The table voltage source can be edited to insert to store reduced data records of any transient response generated by this buck converter.Copies of the table voltage source can be placed into this or any other design in order to display the transient response or apply it to another simulation. This mechanism can be used to test designs that are driven by the buck converter output for their ability to withstand the transient disturbance. Other simulations can be used to compare the simulated response to measured data or to analyze the simulated transient response.Watch for an accompanying blog that will explain how the table voltage source works.

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PWM Loop gain

Norm
Designer43361

Norm

Member for

8 years

328

designs

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groups

Description

To demonstrate data reduction in a PWM design I've copied and modified Mike Donnelly's Buck DC to DC Converter at https://www.systemvision.com/design/buck-dc-dc-converter-switchingI've added a simplified softstart to simulate startup. Sofstart is implemented by ramping up internal voltages over a 5ms period after a 0.5ms delay for a total startup time of 5.5ms. Mike's load transient is timed to activate after steady state. A line transient can be simulated by adding a pulsed voltage source in series with v_line.The total time to simulate startup, steady state and the load transient is set to 10.5ms of which only the final 4ms involve the response to the transient disturbance. Downloaded .csv files of the output voltage (v_out_buck), inductor current (l1inductor/i), or any other signal cover over 84,000 time points.For a 40us switching cycle, a 1us resolution samples each switching cycle 40 times and requires only 4,000 time points to cover the steady state and load transient response. A voltage source is included in the design to mark off this sampling resolution with a sawtooth signal that starts at 6.5ms. The sawtooth appears at the net named x_smpl. Downloading x_smpl along with v_out_buck to Excel enables edits that reduce the original 84,000 time points to 4,000.To demonstrate the data reduction technique for large .csv downloads,t he design includes a dedicated table voltage source which has been preloaded with a set of 4,000 samples from an earlier simulation. The voltage signal vout_reduced displays those 4,000 samples. The table voltage source can be edited to insert to store reduced data records of any transient response generated by this buck converter.Copies of the table voltage source can be placed into this or any other design in order to display the transient response or apply it to another simulation. This mechanism can be used to test designs that are driven by the buck converter output for their ability to withstand the transient disturbance. Other simulations can be used to compare the simulated response to measured data or to analyze the simulated transient response.Watch for an accompanying blog that will explain how the table voltage source works.

About text formats

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