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Craig Beebe's picture



Craig Beebejoined May 21, 2014

posted Monday, February 13, 2017 | 4:13 pm PST

Integrated Projects
Migrating the Libraries
There are three cloud-based component libraries (SVWEBLIB, PARTNERLIB, and USERLIB) that you will need to migrate into your Central Library. Here’s how:

In the Windows Start Menu, search for “Central Library Migrator” and open it
Select File -> Open Library…
Find the .lmc file associated with your integrated project. This is mine: C:\MentorGraphics\PADSVX.2.1\SDD_HOME\standard\templates\SystemVision\CentralLibrary\EDULIB\EDULIB.lmc
Click the “Add symbols…” button along the right
Select each of these three libraries in succession:

C:\MentorGraphics\SystemVision Cloud Import Tool\SVCloudLibraries\PARTNERLIB
C:\MentorGraphics\SystemVision Cloud Import Tool\SVCloudLibraries\SVWEBLIB
C:\MentorGraphics\SystemVision Cloud Import Tool\SVCloudLibraries\USERLIB

Click the Migrate button at the bottom

If all goes well, close and reopen DX Designer, reopen your project and your schematic, and then try importing your design again.
Compiling USERLIB
If the import process displays an error about being unable to import a USERLIB component, the component itself has most likely been imported. You simply need to recompile the USERLIB project. To do so:

Close your current project and open the project C:\MentorGraphics\SystemVision Cloud Import Tool\SVCloudLibraries\USERLIB\USERLIB.prj
In the Navigator window, Simulation tab, open “Simulation, Analysis and Results,” “Model Libraries”, and right click on “HDL Libraries”
Select “Edit Project HDL Library”
Click Add Files and select all models
Check the “Force Compilation” checkbox
Click OK

Close the USERLIB project. If you are using an integrated project, migrate the USERLIB library again (see instructions above). Reopen your project and delete any components that were imported previously. Now your design should import correctly.
Using DMB Components
DMB components should import successfully, but under certain conditions, the simulator may not recognize their property values.
Designs with Buses
Designs with buses should import correctly, but there are some steps you need to take in order to simulate.

In the Navigator window, Simulation tab, open “Simulation, Analysis and Results,” TestBenches, and right click on the name of your schematic
Select “Testbench Options…” and in this dialog, select VHDL for your Netlisting Option
Click OK
In the Navigator window, Simulation tab, open “Simulation, Analysis and Results,” TestBenches, and right click on the name of your schematic
Select “Netlister Header” and in this dialog, check partnerlib, svweblib, and userlib under VHDL Libraries
Click OK
Netlist your design (via Simulation Menu -> Netlist or the “Netlist Design” toolbar button)
Edit the resulting netlist file (found in “Simulation, Analysis, and Results” -> TestBenches, -> Files -> VHDL Files -> .vhd

For each component with a pin that connects to a bus, change the bus name such that it includes the bit range. For example, a 6 bit bus might look like “bus1(0)”. Change this to “bus1(0 to 5)”. If the 6 bit bus looks like “bus1(5)”, change it to “bus1(5 downto 0)”.
Don’t change bits. They should be correct.
Verify the suffix of all user components. The netlist will probably refer to all of them as “DEFAULT,” but this may not be correct. If the name of the corresponding model file begins with something other than “DEFAULT,” change the reference in the netlist file accordingly.
You can also change all “Work” components to “USERLIB” if your USERLIB library contains all of the design’s components and has been compiled.

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