This design is a detailed circuit implementation of the more abstract "state-average" buck converter model shown in the companion design example: “Buck DC to DC Converter vs. Linear Regulator”. This example includes the low-pass voltage sense circuit, an op-amp implementation of the difference amplifier and the lead-lag compensators, as well as PWM switching control of a power MOSFET. Simulation results for the line and load transients, ripple rejection and the power consumption are very similar to the results from the abstract model.
This design uses a number of "datasheet characterized" components, including the power MOSFET (MCH6337), freewheel diode (NRVBA130LT3G) and op-amps (NCV20071), as well as the passive inductor (MSS1583-105KE_) and capacitor (PEG127KA3110Q) of the power stage . The parameter values of these devices were entered directly from the datasheet for the corresponding part, including the "Maximum Ratings" information.
While the simulation time for this switching circuit is significantly longer than for the abstract model, more detailed information about the circuit’s signals and components is available. This includes the component stress levels, which are monitored within all the "datasheet" models. For example, the stress indicator for the power inductor shows that the maximum RMS current level is exceeded under this simulated operating condition (i.e. stress_ratio_current_rms > 1.0).
The companion design, "TDFS Loop Stability for Buck DC to DC Converter - Switching", demonstrates a method to directly assess the open-loop frequency response, and hence the stability margin, of this converter. The TDFS (Time Domain Frequency Sweep) method circumvents the need for state-average models of the switching elements.