Basic Analog

Modeling Basic Analog Components

In this section, the analog component models which make up the PWM Subsystem of the Motor Driver system will be developed. The concepts presented in the previous section will serve as a strong foundation upon which further VHDL-AMS modeling techniques will be introduced.

Analog modeling techniques will be presented in this section. Digital and mixed-analog/digital modeling techniques will be presented in the following sections.

Modeling Approach

The PWM Subsystem is shown again in Figure 1. This subsystem will be implemented using both structural and behavioral modeling approaches. A structural approach is one in which the subsystem is literally modeled as it appears in the figure. This approach requires that models of each of the components be developed and then connected together to form the subsystem.

With the behavioral modeling approach, on the other hand, the entire subsystem will be developed as a single model. This is possible with a capable language such as VHDL-AMS.

Neither of these approaches is always better than the other—it depends on what is being developed, and how it will be used. What is important is to be able to employ either approach as needed, and for the various models work together regardless of which development style is chosen.

Figure 1 - PWM Subsystem.

Analog Component Modeling

For the structural implementation of the PWM Subsystem, a model for each of the individual component models shown in Figure 1 will be developed in turn. Modeling concepts from the previous chapter will be reinforced as these models are developed, and new topics will be introduced as well.

Resistor model

 

A resistor is one of the most fundamental components in any electrical system. The first step required for building a resistor model is to identify a mathematical description that defines the behavior to be implemented. The functionality of a resistor, as well as every other component of the Motor Driver system is described in numerous text books, technical papers, and data sheets.

 

Basic resistor model

 

In the case of simple models such as a resistor, the mathematical description is fairly intuitive. The symbol and governing equation for a simple resistor are shown in Figure 2.

 

Resistor SymbolGoverning Equation

Figure 2 - resistor symbol and equation.

 

At a high, abstract level, a resistor is just a device that enforces Ohm's law, where v is the voltage across the resistor, i is the current through the resistor, and rnom is the nominal (ideal) resistance value of the resistor. The resistor can be modeled in VHDL-AMS as shown in the following listing:


entity resistor is
generic (
rnom : real );    -- resistor value is of type real, and has no default value
port (
    terminal p1, p2 : electrical);
end entity resistor;

architecture ideal of resistor is

 

  quantity v across i through p1 to p2;

 

begin

 

  i == v/rnom;   -- Ohm's law as simultaneous equation

 

end architecture ideal;

 

Since a generalized resistor component will not have a "default" resistance, the model does not include a default value for generic rnom. The value used during simulation is passed in as a parameter from where the resistor model is instantiated into the system model. Both pins of the resistor model are represented as terminal ports of an electrical nature.

 

Quantities v and i are declared to represent the across (voltage) and through (current) aspects of this nature, respectively. These quantities are used to describe Ohm's law in the model architecture.

 

Temperature-dependent resistor model

 

In the previous resistor model, resistance rnom is a constant whose value does not change during a given simulation run. However, it is often desired to predict the effects temperature changes will have on system performance. Since resistors can be quite sensitive to temperature variations, it will be useful to extend the functionality of the resistor model in order to account for this variation. Figure 3 illustrates a resistor with a thermal pin which allows temperature to be fed into it. This temperature is then used in the model to determine the dynamic resistance value.

 

Resistor Symbol (dynamic thermal)Governing Equation

Figure 3 - Dynamic thermal resistor.

 

Resistance can be dynamically calculated as a function of temperature as shown below:

 

 

where rtemp is the resistance value as influenced by temperature,  rcold is the nominal (non-heated) resistance at temperature tempcold, alpha is the linear temperature coefficient for the resistor, temp is the actual temperature, and tempcold is the reference temperature. Note that temperature values are measured in Kelvin be default, but the user is allowed to enter the nominal temperature, tempcold, in Celsius. The model therefore converts tempcold to Kelvin for internal computations. 

 

One of the great benefits of behavioral modeling is that mathematical descriptions of behaviors such as that shown in the above equation can be almost literally copied into the model listing. The VHDL-AMS model listing for the dynamic thermal resistor, r_dynthermal, is given as follows:

 

library IEEE;

 

use IEEE.thermal_systems.all;

 

use IEEE.electrical_systems.all;
 

 

entity r_dynthermal is

 

  generic (

 

    r_cold : resistance;             -- electrical resistance at temp_cold

 

    temp_cold : real := 27.0;    -- calibration temperature (deg C)

 

    alpha : real := 0.0);              -- linear temperature coefficient

 

  port (

 

    terminal p1, p2 : electrical;    -- electrical ports

 

    terminal th1 : thermal);           -- thermal port

 

end entity r_dynthermal;
 

 

architecture linear of r_dynthermal is

 

  quantity v across i through p1 to p2;

 

  quantity r_temp : resistance;

 

  quantity temp across hflow through th1 to thermal_ref;

 

begin

 

  r_temp == r_cold*(1.0 + alpha*(temp - (temp_cold + 273.18)));

 

  v == i*r_temp;

 

  hflow == -1.0*v*i;

 

end architecture linear;

 

As shown, r_temp is calculated continuously as a function of the temperature. This value, in turn, is used as the resistance to calculate voltage and current with Ohm's law (implemented in the form v = i*r, rather than i = v/r—it makes no difference to the simulator which form of the law is used).

 

Note also that a new port has been added. This is a conserved energy port, and so is declared as a terminal. However, unlike ports p1 and p2, which are of an electrical nature, port th1 is of a thermal nature—its across aspect is temperature, and its through aspect is heat_flow.

 

The key to this model is that the conserved thermal properties of this device must be equated to its conserved electrical properties. How can this be accomplished? Recall that heat flow (hflow) is just the rate of movement of energy—which is power. The product of voltage and current is also power. So, quantity hflow can be equated to the product of v and i, and the principles of energy conservation take care of the rest!

 

Resistor model test bench and simulation results

 

Now that the resistor models have been developed, a simulation will be performed on the test circuit given in Figure 4. In VHDL-AMS, a test circuit is referred to as a "test bench." This test bench uses both the basic (r1) and dynamic thermal (r2) resistor models to form a simple voltage divider.

 

The nominal resistance value for both resistors is 50 Ω. The linear temperature coefficient for r2 is 20ppm/°C (20e-6/°C). The DC source is set to 5 V, and the temperature pulse source sends out a pulse that changes from 27 °C to 127 °C. 

 

At the beginning of the simulation, both r1 and r2 are the same value (50 Ω) while the temp_in output value is the ambient temperature (27°C).

 

Figure 4 - Voltage divider with resistor and r_dynthermal. 

 

The temperature source outputs the temperature pulse, temp_in (middle waveform), which heats up the resistor. r2’s temperature-dependent resistance r_temp, (bottom waveform) increases, which raises the voltage measured at v_out (top waveform). In this example, v_out starts out at exactly one-half of v_in (2.5 V). However, as the temp_in waveform ramps to 127 °C, the dynamic resistance increases to 50.1 Ω, causing a corresponding increase in v_out from 2.5 V to 2.5025 V.

 

Capacitor model

 

A capacitor is another fundamental component in any electrical system. To build a capacitor model, a mathematical description that defines its behavior must again be determined.

 

Basic capacitor model

 

The symbol and governing equation for a capacitor model is given in Figure 5.

 

Capacitor SymbolGoverning Equation

Figure 5 - Capacitor symbol and equation.

 

A capacitor can be modeled in VHDL-AMS as follows:

 

entity c_basic is

 

  generic (

 

     cnom : real );   -- capacitor value is of type real, and has no default value

 

  port (

 

    terminal p1, p2 : electrical);

 

end entity c_basic;

 

 

 

architecture ideal of c_basic is

 

  quantity v across i through p1 to p2;

 

begin

 

  i == cnom*v'dot; -- characteristic equation

 

end architecture ideal;

 

As with the generalized resistor, a generalized capacitor does not have a default capacitance value, and so the model does not include a default value for generic cnom. Both pins of the capacitor model are represented as terminal ports of an electrical nature.

 

Quantities v and i are declared to represent the across (voltage) and through (current) aspects of this nature, respectively. These quantities are used to describe the capacitor's governing equation in the model architecture.

 

The VHDL-AMS modeling language provides a mechanism for getting information about objects in a model. Several predefined attributes are available for this purpose.

 

In the capacitor model, the predefined attribute ‘dot is used to return the derivative of quantity v. Thus i will continuously evaluate to the derivative of v (multiplied by cnom).

 

Other popular predefined analog attributes include ‘integ (integration), ‘delayed (delay), and ‘ltf (Laplace transfer function). The ‘ltf  attribute will be used in the low-pass filter model discussed shortly.

 

Capacitor with equivalent-series resistance (ESL)

 

Sometimes it is necessary to include special characteristics into what would otherwise be a basic component model. Adding the dynamic temperature-dependent characteristics to the resistor model was an example of this.

 

Physical capacitor components exhibit a certain amount of inductance in addition to capacitance. This is referred to as equivalent-series inductance, or ESL. For certain applications, the inclusion of the ESL effect can be the difference between catching a potential design problem or missing it altogether.

 

One of the powerful features of hardware description languages is the ease with which models can be modified to account for new behaviors. The modification shown in the following equation needs to be made to the characteristic equation of the basic capacitor model in order to include ESL.

 

 

Note that the capacitor equation has been re-formulated to solve for voltage in terms of current. This was done so that the voltage due to capacitance could be directly summed with the voltage due to ESL. The VHDL-AMS listing for the capacitor model with ESL is given as follows:

 

entity cap_esl is

 

  generic (

 

     cnom : real )   -- capacitor value is of type real, and has no default value

 

     esl : real := 0.0);  -- equivalent-series inductance, default value = 0

 

  port (

 

    terminal p1, p2 : electrical);

 

end entity cap_esl;

 

 

 

architecture ideal of cap_esl is

 

  quantity v across i through p1 to p2;

 

begin

 

  v == (1.0/cnom)*i'integ + esl*i'dot;          -- characteristic equation

 

end architecture ideal;

 

As shown in the listing, the only real changes from the basic capacitor model are the inclusion of the ESL effect in the characteristic equation, as well as the inclusion of ESL as a generic constant to be passed into the model.

 

Since it is reasonable to assume that this capacitor could also be used without the ESL effect, we give it a default ESL value of zero. In this way, the model can be used as a basic capacitor by default, yet can also be parameterized for ESL when required.

 

Capacitor model test bench and simulation results

 

The performance of the two capacitor model implementations is illustrated with the test bench shown in Figure 6. The simulation results show that a physical system represented by this model would experience a glitch at about 1 us. However, if a capacitor model without the ESL effect were to be used in the system model, this glitch would not be detected, as shown by the signal a_d_cap_out. On the other hand, with ESL effects represented in the model, the glitch is detected in the simulation, as shown by signal a_d_cap_esl_out.

 

Figure 6 - Capacitor models test bench.

 

Low-pass filter model

 

In order to illustrate the range of potential modeling choices available with VHDL-AMS, the low-pass filter will be described using three techniques: Laplace transfer function, differential equation, and structural RC (resistor/capacitor) components.

 

Low-pass filter (transfer function)

 

Filter behavior is often described using Laplace transfer functions. The description of the low-pass filter behavior using a Laplace transfer function is given in Figure 7.

 

LPF SymbolGoverning Equation

Figure 7 - Low-pass filter symbol and equation.

 

In the figure, wp is the cutoff frequency in radians per second (rad/s). The equation represents a low-pass filter as a Laplace transfer function with the DC gain normalized to K. Laplace transfer function descriptions are extremely useful for device behaviors that are described by 2nd or higher-order differential equations.

 

This low-pass filter equation may be implemented directly using VHDL-AMS. The complete VHDL-AMS model for the low-pass filter is listed as follows:

 

library IEEE;

 

use IEEE.electrical_systems.all;

 

use IEEE.math_real.all;

 

 

 

entity LowPass is

 

  generic (

 

    Fp : real := 1.0e6;   -- pole frequency [Hz]

 

    K : real := 1.0);        -- filter gain

 

  port (terminal input : electrical;

 

           terminal output : electrical);

 

end entity LowPass;

 

 

 

architecture s_dmn of LowPass is

 

  quantity vin across input to electrical_ref;

 

  quantity vout across iout through output to electrical_ref;

 

  constant wp : real := math_2_pi*Fp;        -- convert Hertz to rad/s

 

  constant num : real_vector := (wp, 0.0);  -- numerator expression
  constant den : real_vector := (wp, 1.0);   -- denominator expression

 

begin

 

  vout == K * vin'ltf(num, den);   -- Laplace equations   

 

end architecture s_dmn;

 

This low-pass filter implementation uses the VHDL-AMS ‘ltf (Laplace transfer function) attribute to implement the transfer function in terms of num (numerator) and den (denominator) expressions. These expressions must be constants of type real_vector. Constants are used in a manner similar to generics, but they are declared in the architecture, and are thus (purposely) not intended to be changed by a general model user. If a constant is intended to be changed by a model user, it should be declared as a generic in the entity.

 

The real vectors are specified in ascending powers of s, where each term is separated by a comma. Since num and den must be of type real_vector, these vectors must contain more than one element. However, for the low-pass filter, numerator num only contains a single element, so a second element, 0.0, is added to satisfy the multiple element restriction.

 

The low-pass filter term from the equation in Figure 9 is declared as constant wp, in rad/s. Since the user specifies a cutoff frequency in Hertz (Fp), a conversion from Hertz to rad/s is performed, the result of which is assigned to wp. Constant math_2_pi is used for this conversion. It is defined along with many other math constants in the IEEE.math_real package, which must be included in the model description in order for items within it to be accessed by the model.

 

The ‘ltf attribute is a very powerful and convenient tool for describing Laplace transfer functions. It is particularly useful for describing higher-order systems, which can be difficult to express using time-based equations.

 

The ports of the low-pass filter model are declared as electrical terminals. This allows for the discrete component implementation of the filter (discussed shortly) to be directly substituted for the Laplace transfer function implementation in the system model.

 

In addition to a Laplace transfer function-based implementation, a single pole low-pass filter can also easily be expressed as a differential equation as well as a Laplace transfer function. This is illustrated next.

 

Low-pass filter (differential equation)

 

By rearranging the equation from Figure 9 and replacing the Laplace operator s with the differential operator d/dt, the low-pass filter action can also be realized in terms of a differential equation, as shown below:

 

 

Since this equation is time-based, the pole frequency must be converted into a time constant. This conversion is shown below:

 

 

where tp is the time constant in seconds.

 

The VHDL-AMS model listing using the differential equation is shown as follows:

 

library IEEE;

 

use IEEE.electrical_systems.all;

 

use IEEE.math_real.all;

 

 

 

entity LowPass is

 

  generic (

 

    Fp : real := 1.0e6;   -- pole frequency [Hz]

 

    K : real := 1.0);       -- filter gain

 

  port (terminal input : electrical;

 

           terminal output : electrical);

 

end entity LowPass;

 

 

 

architecture diff_eq of LowPass is

 

  quantity vin across input to electrical_ref;

 

  quantity vout across iout through output to electrical_ref;

 

  -- convert pole frequency to time constant

 

  constant tp : real := 1.0/(math_2_pi*Fp);  

 

begin

 

  vin == (vout + tp*vout'dot)/K;  -- time-based equation          

 

end architecture diff_eq;

 

In this listing, the pole (cutoff) frequency is still specified in Hertz for the convenience of the model user. It is converted to a time constant in the architecture.

 

This listing also illustrates that the independent variable, vin, can be on the left-hand side of the differential equation, while the dependent variable, vout, is on the right-hand side. This equation-building flexibility allows for convenient mathematical formulation and implementation of device behaviors.

 

One last point to note is that the diff_eq architecture can be implemented in the same model as the s_dmn architecture. Models often have multiple architectures, one of which the user will choose at simulation time. This is desired so the actual model symbol in the schematic will not need to be replaced when switching between the various implementations.

 

Low-pass filter (structural)

 

Both the differential equation and Laplace transfer function approaches for describing the low-pass filter behavior are relatively straightforward and commonly used in practice. The low-pass can also be implemented structurally as an active filter using discrete RC (resistor/capacitor) components and an op amp. The relationship between the time constant and RC component values is shown below:

 

 

The structural implementation of the low-pass filter and corresponding equation are illustrated in Figure 8. Components R and C from Equation (5) are implemented as RFB and CFB in the figure. In this configuration, the low-pass filter is realized by a frequency-dependent voltage divider. As frequency goes up, capacitor reactance goes down, and the gain of the op amp drops. At DC, the gain is equal to RFB/RIN.

 

LPF (RC)Governing Equation

Figure 8 - Structural low-pass filter.

 

The structural “netlist” of this model implementation is shown as follows:

 

library IEEE;

 

library edulib;

 

use IEEE.electrical_systems.all;

 

use work.all;

 

 

 

entity LPF is

 

end entity LPF;

 

 

 

architecture arch_LPF of LPF is

 

   terminal VIN : ELECTRICAL;

 

   terminal VRT_GND : ELECTRICAL;

 

   terminal VOUT : ELECTRICAL;

 

 

 

begin

 

 

 

   R1 : entity WORK.RESISTOR(IDEAL)

 

      generic map ( RNOM => 15.9E3 )

 

      port map ( P1 => VRT_GND,

 

                           P2 => VOUT );

 

 

 

   V_PULSE1 : entity EDULIB.V_PULSE(IDEAL)

 

      generic map ( AC_MAG => 1.0,

 

                    PERIOD => 10 MS,

 

                    PULSE => 5.0,

 

                    TI2P => 100 US,

 

                    TP2I => 100 US,

 

                    WIDTH => 5 MS )

 

      port map ( POS => VIN,

 

                           NEG => ELECTRICAL_REF );

 

 

 

   C1 : entity WORK.C_BASIC

 

      generic map ( CNOM => 0.1E-6 )

 

      port map ( P1 => VRT_GND,

 

                  P2 => VOUT );

 

 

 

   R2 : entity WORK.RESISTOR(IDEAL)

 

      generic map ( RNOM => 15.9E3 )

 

      port map ( P1 => VIN,

 

                           P2 => VRT_GND );

 

 

 

   U1 : entity WORK.OPAMP_3P

 

      port map ( IN_POS => ELECTRICAL_REF,

 

                           IN_NEG => VRT_GND,

 

                           OUTPUT => VOUT );

 

 

 

end architecture arch_LPF;

 

The various models are instantiated by library and name. For example, the resistor model’s entity is named “RESISTOR”, and it is located in the “WORK” library, which is the default library into which the models of a design will be compiled. The V_PULSE model, on the other hand, is located from a library called “EDULIB”, which is an educational model library that is included with SystemVision. The architecture is optionally specified as well (in parentheses) after the entity.

 

Keywords generic map are used to map externally supplied values to model generics. Each resistor, for example, has the value 15.9e3 mapped to the model generic, RNOM.

 

Similarly, keywords port map are used to map external nets (nodes) to model ports. For example, port P1 of resistor R1 is mapped to node VRT_GND, and port P2 is mapped to node VOUT.

 

Note that the structural netlist itself is essentially a VHDL-AMS model. The only real difference between the netlist and a component model is that the netlist entity does not typically require ports or generic constants.

 

VHDL-AMS provides tremendous modeling flexibility by allowing both detailed model behavior as well as structural netlists to be described using the same language. In fact, detailed modeling statements can be freely mixed in a structural netlist description as well, providing even greater power to the model user.

 

Low-pass filter model test bench and simulation results

 

The low-pass filter test bench is shown in Figure 9. This test bench consists of all three model implementations described earlier. The top symbol in the test bench is the low-pass filter with the Laplace transfer function architecture selected; the middle symbol is the low-pass filter with the differential equation architecture selected; and at the bottom is the structural implementation of the low-pass filter. All three implementations are parameterized for a DC gain = 1, and a pole (-3 dB) frequency of 100 Hz.

 

The simulation results for a frequency domain analysis reveal that all three models have a measured -3 dB gain value at a frequency of 100 Hz.

 

Figure 9 - Test bench and waveforms for low-pass filter implementations.

 

We have shown how the behavior of a simple low-pass filter can be modeled using three techniques: Laplace transfer functions, differential equations, and structurally building the model using individual component models. All of these models can be simulated in either the time or frequency domains.

 

Op amp model

 

The structural implementation approach used in the development of the low-pass filter model employs an op amp component. A component model for the op amp will be considered next.

 

Op amps are key building blocks for analog designs. The PWM Subsystem uses an op amp for two major purposes: to sum the input command voltage with the sawtooth waveform and to implement the low-pass filter discussed in the previous section.

 

For this application, a general purpose op amp will be sufficient (i.e. specialized op amp characteristics such as low-noise or high-bandwidth are not required). Therefore, an idealized op amp will be modeled.

 

What does "idealized" mean? An op amp is at its core a bandwidth-limited high gain block. In fact, it is in principle very similar to the low-pass filter discussed in the previous section. The symbol and governing equation for the basic op amp model are given in Figure 10.

 

Op Amp SymbolGoverning Equation

Figure 10 - Op amp symbol and governing equation.

 

The governing equation for the op amp looks quite similar to that of the low-pass filter shown in Figure 9. In fact, the only significant difference is that gain K in the low-pass filter equations has been replaced by the open-loop gain of the op amp, AOL.

 

Basic op amp

 

The following listing illustrates a basic op amp as defined in the equation given in Figure 13:

 

library IEEE;

 

use IEEE.math_real.all;

 

use IEEE.electrical_systems.all;

 

 

 

entity OpAmp_3p is

 

  generic (a_ol : real := 100.0e3;  -- open loop gain

 

                 f_0dB : real := 1.0e6    -- unity Gain Frequency [Hz] );

 

port (

 

    terminal in_pos, in_neg, output : electrical);

 

end entity OpAmp_3p;

 

 

 

architecture basic of OpAmp_3p is

 

  constant f_3dB : real := f_0dB / a_ol;            --   -3dB frequency

 

  constant w_3dB : real := math_2_pi*f_3dB;  --   -3dB freq in rad/s

 

  constant num : real_vector := (0 => a_ol);

 

  constant den : real_vector := (1.0, 1.0/w_3dB);  -- ascending order

 

  quantity v_in across in_pos to in_neg;

 

  quantity v_out across i_out through output;

 

begin

 

  v_out == v_in'ltf(num, den);  -- output voltage

 

end architecture basic;

 

As mentioned earlier, the basic op amp implementation is quite similar to that of the transfer function implementation of the low-pass filter. The two main differences are:

 

·         The op amp model has two input pins, and the input voltage is taken as the differential voltage across these pins.

 

·         The low-pass pole location, f_3dB, is calculated as the ratio of the unity gain frequency, f_0dB, and the open loop gain, a_ol. This change was made to accommodate parameterizing the op amp model with data in the same form it would likely appear in a datasheet.

 

Op amp with input and output resistance

 

The basic op amp model will now be extended so that it can be parameterized with real input and output resistance values. This can be done by making the following changes to the basic model:

 

In the entity, add an input resistance generic:

 

        r_in  : resistance := 1.0e6;    -- input resistance [Ohms]

 

In the architecture, declare the input current through quantity:

 

        quantity v_in across i_in through in_pos to in_neg;

 

Add an equation that governs the new behavior (Ohm's law):

 

        i_in == v_in / r_in;                       -- input current

 

Similarly, to model the op amp's output resistance, the following changes are made:

 

In the entity:

 

        r_out : resistance := 100.0;    -- output resistance [Ohms]

 

In the architecture:

 

        v_out == v_in'ltf(num, den) + i_out*r_out;  -- output voltage

 

The complete architecture will then appear as:

 

architecture res_in_out of OpAmp_3p is

 

  constant f_3dB : real := f_0db / a_ol;            --  -3dB frequency

 

  constant w_3dB : real := math_2_pi*f_3dB;  --  -3dB freq in rad/s

 

  constant num : real_vector := (0 => a_ol);

 

  constant den : real_vector := (1.0, 1.0/w_3dB);

 

  quantity v_in across i_in through in_pos to in_neg;

 

  quantity v_out across i_out through output;

 

begin

 

  i_in  == v_in / r_in;  -- input current

 

  v_out == v_in'ltf(num, den) + i_out*r_out;  -- output voltage

 

end architecture res_in_out;

 

Op amp model test bench and simulation results

 

An open-loop op amp configuration is shown in the test bench in Figure 11. For this test bench, the input voltage is +/- 50 uV. The op amp input resistance is specified as 1.0e6 Ω, and the output resistance is specified as 100.0 Ω. The open-loop gain is parameterized to 100.0e3, and the unity gain frequency is set to 1.0e6. The load resistor is set to 0.1 Ω.

 

For a frequency domain analysis, we would expect a “loaded” open-loop gain of 100 (40 dB), which is the product of AOL and r_load/(r_out + r_load). This is calculated as 100,000.0*0.1/(0.1 + 100.0) ~= 100.0. We would expect a cutoff frequency of 10 Hz (unity gain frequency divided by open-loop gain). This is what the simulation results show.

 

The upper waveform for the time domain results shows the input current drawn by the op amp, which is measured at approximately 50 pA. This makes sense for a 1.0e6 Ω input resistance (50 uV/1.0e6 Ω = 50 pA).

 

The lower waveform shows the output current with a 100 Ω output resistance.  The output current measures 50 mA, which also is expected (Vin*AOL/ROUT= 50 uV*100.0e3/100 = 50 mA).

 

Figure 11 - Test bench and waveforms for op amp model.

 

 

 

/ Created Feb 7, 2018 | 5:11 pm Last Updated 1 year 11 months ago